1. Field
The present disclosure relates to electronic integrated circuits (ICs), and more specifically to Silicon on Insulator (SOI) ICs.
2. Description of Related Art
Reducing the size of ICs is important for improving economy of fabrication and packaging. Also, for some applications, such as RF ICs for wireless mobile units, the ICs must be small because the unit in which they are incorporated is small, and the space available for the ICs is constrained. However, reducing the size of ICs can be difficult for various reasons. For regions of an IC comprising primarily active components (e.g., transistors), for example, heat dissipation from the IC is made more difficult because the area for thermal coupling is reduced. For regions of an IC comprising primarily passive components (such as capacitors and inductors), the inherent size of the components is related to physical principles, and reducing their size is difficult to achieve.
For RF circuits (such as RF power amplifiers (PAs) and RF switches), the space required for passive components can be a major contribution to the overall size of the circuit because RF circuits frequently require RF filters and/or resonators, which have large passive elements. Typically, more than half the area of an RF circuit is allocated to such passive components. A further problem is presented by the placement of passive components. In some implementations, the passive components are placed “off-chip” (i.e., circuit components that are separate from the RF ICs comprising the active components) because it is not practical to integrate the passive components on-chip for reasons relating to component size, efficient signal coupling, or other considerations. In other implementations, the passive components are placed on-chip in regions of the IC that are separate from the active switching components. In either case, a relatively large IC area is required for the passive components, and achieving efficient RF signal coupling between the active and passive components is difficult because of parasitic impedances associated with interconnects and requirements for impedance matching for signals conveyed between the active and passive components.
According to prior art techniques, a method for reducing the size of ICs is to vertically stack one or more layers of IC components. For example, first IC components may be fabricated on a substrate, and a second layer of IC components may be fabricated on top of the first IC layer, wherein the component layers are separated by an insulating layer, and electrically connected using vias (i.e., holes filled with conductive material) that pass through the insulating layer. However, for RF ICs in particular, the stacking approach has many limitations. For example, using vias for electrical interconnects may be difficult to implement for RF ICs because of impedance matching and parasitic losses associated with the vias. Another problem is presented by the processes for producing stacked ICs because these processes involve non-standard IC processing steps. This results in reduced yields and increased costs of production.
The added layers in stacked ICs also reduce thermal conductivity, and removing heat generated by active devices is thereby impeded. Also, further IC layer stacking may increase the thickness of the ICs sufficiently to preclude use in systems requiring low package profiles.
For reasons well known to persons skilled in the arts of RF IC design, RF ICs may be advantageously implemented using silicon-on-insulator (SOI) technology. For some applications, SOI RF ICs may be fabricated on commercially available SOI wafers comprising a silicon substrate, a buffer layer (typically a buried-oxide (BOX) silicon dioxide layer) bonded to the substrate, and a thin silicon layer (referred to herein as the “active layer”) on top of the buffer layer. Devices such as transistors may be fabricated in the active layer, and the buffer layer provides electrical isolation between IC components. However, because the buffer layer is relatively thin (with a typical thickness less than a micrometer), capacitive coupling of RF signals between devices in the active layer and the conductive silicon substrate may cause poor performance for many types RF ICs. For these purposes, replacing the silicon substrate with a fully insulating substrate may be advantageous. The limitations discussed above with respect to reducing the size of RF ICs in general also relate specifically to SOI RF ICs.
Some exemplary limitations of prior art are presented in the following reference: U.S. patent application Ser. No. 12/612,957, Kerry Bernstein, et al., entitled “Double-Sided Integrated Circuit Chips,” published Feb. 25, 2010 as U.S. Publication No. 2010/0044759 A1. U.S. application Ser. No. 12/612,957 (hereby incorporated herein as if set forth in full) teaches an IC structure and fabrication method wherein two SOI ICs are fabricated separately on SOI wafers having BOX layers. The two SOI ICs are thinned to expose the BOX layers, and bonded back-to-back by joining the BOX layers. The two circuits of the two SOI ICs are electrically coupled together using vias formed through the BOX layers. One limitation of the referenced teachings is that the composition of the layer that separates the two circuits is constrained to be silicon dioxide, which comprises the BOX layers. Silicon dioxide has poor thermal conductivity, and other materials would provide superior performance especially for RF power amplifier or switching circuits. Another limitation of the prior art teachings results from the expensive methods required to align and fabricate the vias. A further limitation of the prior art teachings is that circuit failure and malfunction may occur due to faulty vias.
The present teachings disclose novel ICs, and fabrication methods that overcome limitations of prior art by reducing IC areas and thicknesses, improving IC performance, and providing efficient and economical methods of fabrication.